| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| resistor [2012/07/01 20:53] – mcmaster | resistor [2013/10/20 14:59] (current) – external edit 127.0.0.1 |
|---|
| ====== Always on transistor ====== | ====== Depletion load ====== |
| |
| These are arranged with the transistor tied to be always on. A MOSFET is classified into 3 areas of operation: | FIXME: compare with analysis at [NMOS logic design], tried to do for enhancement mode and so analysis didn't work out |
| * Cutoff (VGS < Vth): little conduction | |
| * Triode (VGS > Vth and VDS < (VGS - Vth)): resistive | |
| * Saturation (VGS > Vth and VDS > (VGS - Vth)): conductive | |
| |
| Say with an N-MOSFET you tie the gate to drain to VDD. VGS > Vth (say VDD is 5V and Vth is 3V) which takes out cutoff. Say that the circuit tried to apply 0V to this node. How would the resistor react? VDS is now 5V and VGS -Vth = 5V | Most MOSFETs encountered are enhancement. In essence a its off if you don't apply any voltage between gate and source and fully on if you apply lots of voltage between drain and source and a little between the gate and source (ie switching a high voltage load). However, there are also depletion mode transistor which have essentially the opposite behavior: they are normally on with VGS = 0. |
| |
| Pulldown resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http://www.4004.com): | Depletion load PMOS resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http://www.4004.com): |
| |
| {{:flylogic:intel_400:pullup_metal_flylogic.png}} | {{:flylogic:intel_400:pullup_metal_flylogic.png}} |
| {{:intel_4004:pullup_mask_cif.png?150}} | {{:intel_4004:pullup_mask_cif.png?150}} |
| |
| | Which translates to the following schematic: |
| | |
| | {{:mcmaster:resistor:pmos_pulldown_sch.png}} |
| | |
| | So the natural question to ask is how do you tell a depletion from an enhancement load MOSFET? For a non-obfuscated digital design typically only depletion mode transistors have this configuration and are enhancement otherwise. Like this, once you get into analog all bets are off and you need to be careful. |
| |
| |
| - Resistor Fabrication on Semiconductor Wafers: http://www.siliconfareast.com/resistor-fab.htm | - Resistor Fabrication on Semiconductor Wafers: http://www.siliconfareast.com/resistor-fab.htm |
| - http://uvicrec.blogspot.com/2011/09/understanding-intel-4004.html | - http://uvicrec.blogspot.com/2011/09/understanding-intel-4004.html |
| | - NMOS logic design: http://www.ittc.ku.edu/~jstiles/312/handouts/section_10_4_NMOS_Logic_Design_package.pdf |
| | |
| |
| |
