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resistor [2012/07/01 22:07] – mcmaster | resistor [2012/07/01 22:37] – mcmaster | ||
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====== Depletion load ====== | ====== Depletion load ====== | ||
- | These are arranged | + | FIXME: compare |
- | * NMOS | + | |
- | * Cutoff (VGS < Vth): little conduction | + | |
- | * Triode (VGS > Vth and VDS < (VGS - Vth)): resistive | + | |
- | * Saturation (VGS > Vth and VDS > (VGS - Vth)): conductive | + | |
- | * PMOS | + | |
- | * Cutoff (VGS > Vth): little conduction | + | |
- | * Triode (VGS < Vth and VDS > (VGS - Vth)): resistive | + | |
- | * Saturation (VGS < Vth and VDS < (VGS - Vth)): conductive | + | |
- | In essence a MOSFET is off if you don't apply any voltage between gate and source. Its fully on if you apply lots of voltage between drain and source and a little between the gate and source (ie switching a high voltage load). | + | Most MOSFETs encountered are enhancement. |
- | Pulldown | + | Depletion load PMOS resistor on Intel 4004 (IC images courtesy of Flylogic, mask from http:// |
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- | (FIXME: compare with analysis at [NMOS logic design] The metal is VDD (-10V). | + | So the natural question to ask is how do you tell a depletion from an enhancement load MOSFET? |