Tutorial

Practical tips

support: syntax features supported in particular tools

looping (generate/for)

named_block

Misc

Looping

This works in xst:

for (integer ii=0; ii<`SATA_GTX_DEBUG_N; ii=ii+1) begin

but makes xst unhappy:

WARNING:HDLCompiler:1490 - "my.v" Line 831: Loop valiable declaration is not allowed in this mode of verilog

I like it because it reduces scope. I had trouble passing flags to make it happy. Legal in SystemVerilog?

Unused wires

Verilog has .() to explicitly indicate unuconnected signals in a module. What about global signals? Synder reccomends somehting like this:

wire _unused = &{
    my_unused_wire,
    my_unused_array_bit[3],
    ...
    1'b0};

_FCKG_BLANK_TD_

And then filter out _unused

To take this a step further, I realized that xst 14.5 takes this:

wire _unused = &{_unused
    my_unused_wire,
    my_unused_array_bit[3],
    ...,
    1'b0};

_FCKG_BLANK_TD_ I don't know if this will work on other tools but it produces no warnings in either xst nor my linter (Eclipse Verilog). However, while it elimianted the unused warnings from the linter, it did not remove the unused warnings from xst.

The choice of & vs | is probably arbitrary

References / reccomended reading

 
verilog/start.txt · Last modified: 2016/06/09 20:00 by mcmaster
 
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