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Dealing with PLL lock

MIG 1.9 u_iodelay_ctrl:

// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
//  localparam RST_SYNC_NUM = 25;
...
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;

always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
  if (rst_tmp_idelay)
    rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
  else
    rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;

assign rst_ref  = rst_ref_sync_r[RST_SYNC_NUM-1];

References

reset.txt · Last modified: 2013/11/05 16:40 by sky