Xilinx

Xilinx IP cores like to do like this (example from MIG 1.9 XADC):

// Reset sync
(* ASYNC_REG = "TRUE" *)  reg rst_r1;
(* ASYNC_REG = "TRUE" *)  reg rst_r2;
                                            
// Synchronization rst to XADC clock domain
always @(posedge xadc_clk) begin
    rst_r1 <= rst;
    rst_r2 <= rst_r1;
end

ASYNC_REG appears to affect simulation only. UG625 says: “The ASYNC_REG (Asynchronous Register) constraint:

  • Is a timing constraint.
  • Is used to improve the behavior of asynchronously clocked data for simulation.
  • Disables X propagation during timing simulation. In the event of a timing violation, the previous value is retained on the output instead of going unknown.”

References / papers

 
cdc.txt · Last modified: 2013/11/05 13:12 by sky
 
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