Table of Contents

This page lists aggressive Verilog syntax and how tools responded to it. Aggressive may be:

If one version is shown to work or not work, list it and don't list any additonal versions unless its found to work on some versions but not others.

xst tests are in Verilog 2001 mode

TODO:

Markings:

Function

Construct Altera (quartus_map) IVerilog (iverilog) Synopsis (synplify) Verilator (eclipse) Xilinx ISE (xst) Xilinx iSim (fuse) Yosys Notes
res = my_func(1, 2); 0.9.5: Y Y 14.5 (P.58f): Y 14.5 (P.58f): Y Vanilla syntax, should be pretty safe to use
res = my_func(.a(1), .b(2));
0.9.5: N

(error: invalid module item.)
N 14.5 (P.58f): Y
14.5 (P.58f): N

(Internal Compiler Error in file ../src/VlogExpr.cpp at line 3735)
Nice but poor portability. Only use with good reason
input [7:0] a; 0.9.5: Y Y 14.5 (P.58f): Y 14.5 (P.58f): Y Vanilla syntax, should be pretty safe to use
input wire [7:0] a;
0.9.5: N

(int VLparse(): Assertion `current_function == 0' failed)
Y 14.5 (P.58f): Y 14.5 (P.58f): Y No real advantage, consider not using

Verilator ignores all errors within a function definition (sounds like a bug…)

Named block

Construct Altera (quartus_map) IVerilog (iverilog) Synopsis (synplify) Verilator (eclipse) Xilinx ISE (xst) Xilinx iSim (fuse) Yosys
\_scope\`LINE
0.9.5: N?

(main.v:19: warning: macro LINE undefined (and assumed null) at this point.)
Y 14.5 (P.58f): Y 14.5 (P.58f): Y
generate if (1) begin : scope 0.9.5: Y Y 14.5 (P.58f): Y 14.5 (P.58f): Y
if (1) begin : scope 0.9.5: Y N 14.5 (P.58f): Y 14.5 (P.58f): Y
begin : scope
0.9.5: N

(invalid module item.)
N 14.5 (P.58f): Y 14.5 (P.58f): Y
scope : begin
0.9.5: N

(Invalid module instantiation)
N 14.5 (P.58f): Y 14.5 (P.58f): Y

Mux

Construct Altera (quartus_map) IVerilog (iverilog) Synopsis (synplify) Verilator (eclipse) Xilinx ISE (xst) Xilinx iSim (fuse) Yosys Notes

Unused

Construct Altera (quartus_map) IVerilog (iverilog) Synopsis (synplify) Verilator (eclipse) Xilinx ISE (xst) Xilinx iSim (fuse) Yosys Notes
wire _unused = &{my_signal, 1'b0}; Y Y, but produces _unused warning
wire _unused = &{_unused, my_signal, 1'b0}; Y Y, but does not eliminate my_signal warning


 
verilog/support.txt · Last modified: 2015/04/20 15:57 by mcmaster-guest
 
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution 4.0 International
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki