One major hole in Verilog 2001 is that it has no equivilent of VHDL's “record” or C's “struct”. SystemVerilog adds struct but isn't availible on xst. Page playing around with various ways to group signals both in and outside of modules.

Listly very loosely in order of preference and/or popularity

Use SystemVerilog

If this is an option, use the “struct” type and you are done

Copy and paste

The current state of the art: copy the signals you need everywhere they need to be repated. Are your connecting modules 10 levels deep in your heirarchy and you added some signals? Better make sure your control key is oiled.

Construct/deconstruct signals as busses

Ex: ChipScope does this. As you pass signals from one module toa nother, declare it as an inout bus

For extra points, make a module that takes the signal in and can spit out input/output signals.

Here's a trivial example:

//No typedef in Verilog
`define MY_GROUP_BUS    wire [3:0]
module my_group (
        inout `MY_GROUP_BUS bus,
        input wire i_A, output wire o_A
        input wire i_B, output wire o_B,
        input wire [1:0] i_C, output wire [1:0] o_C);
    assign bus[0] <= i_A;
    assign o_A <= bus[0];
    
    assign bus[1] <= i_B;
    assign o_B <= bus[1];

    assign bus[3:2] <= i_C;
    assign o_C <= bus[3:2];
endmodule

module a_module (input wire CLK, inout `MY_GROUP_BUS bus);
    reg A;
    wire [1:0] C;
    my_group group(.bus(bus), .i_A(A), .o_C(C));

    always @(posedge CLK) begin
        A <= C[0] && C[1];
    end
endmodule

In above, a_module used signals A and C but not B (which may be used in a submodule or other modules).

This can also be similiary used for FSM to generate synchronous and asynchronous portions within a module.

With some AGC to generate the glue modules this could be a reasonable option

Verilog preprocessor

Theory: use preprocessor defines to group busses. Best case: if Verilog pre-processor can do C's X macros, it might be a viable option

Havne't explored this in detail

Automatically generated code (AGC)

Also an option but ugly to interleave into the language (ie by using a custom preprocessor in Python, perl, etc)

Module as a data structure

Theory: according to LRM IIRC, you can reach into modules in theory. In practice I never see anyone do this. Could we create modules as objects to use to group signals?

My test code looked something like this:

module fsm_state (wire _unused); //was it the lack of input/output that crashed xst?
    reg a;
    reg b;
    
    //XST didn't like modules without input/output
    assign _unused = a && b;
endmodule

module project_top (
        input wire A,
        input wire ACLK
        output wire C);
    fsm_state state_cur();
    fsm_state state_next();
    reg m;
    reg n;
    reg x;

    always @(posedge ACLK) begin
        m <= n;
        x <= state_next.a;
        //state_cur.a <= state_next.a;
    end
endmodule

This was creative but didn't end well:

INTERNAL_ERROR:Xst:cmain.c:3423:1.29 -  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.  

While I had a lot of problems with the ISE GUI crashing (mostly before it stabalized when they stopped developing it in favor of Vivado), I've rarely had the command line tools crash on me

 
verilog/signal_group.txt · Last modified: 2015/03/04 13:26 by mcmaster-guest
 
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