Constructs used to repeat things

generate

Use generate when you need to instantiate multiple components

Simple example:

module stuff # (
        parameter PATGEN=1) (
        output reg [7:0] o_data);
    generate if (PATGEN) begin
        my_patgen my_patgen(o_data);
    end else begin
        my_patgen = 8'b0;
    end endgenerate
endmodule

Example: global_flags is an array of events that we want to count in the clk1 domain. Generate an array of synchronizers that are fed into counters in a different clock domain (clk2)

wire [31:0] global_flags;
reg [31:0] global_counters [15:0];
genvar gi;
generate
    for (gi = 0; gi < 16; gi = gi + 1) begin: MY_BLOCK
        wire gen_wire;
        
        my_synchronizer sync(
                .clk_a(clk1), .data_a(global_flags[gi]),
                .clk_b(clk2), .data_b(gen_wire));
    
        always @(posedge clk2) begin
            if (gen_wire) begin
                global_counters[gi] = global_counters[gi] + 1'b1;
            end
        end
    end
endgenerate

It is supposedly possible to use generate inside an always block but I haven't had good results and favor for

for

Use to loop within an always block

Example: increment a per-address counter when an address in a particular range is selected (there are simpler ways to do this)

reg [31:0] counters [15:0];
wire [15:0] i_addr;
always @(posedge clk) begin
    for (integer i=0; i<16; i=i+1) begin
        if (i_addr == `ADDR_BASE + i) begin
            counters[i] = counters[i] + 1'b1;
        end
    end
end
 
verilog/looping.txt · Last modified: 2015/01/20 17:28 by mcmaster-guest
 
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