You should typically use non-blocking unless you have a very good reason to use blocking: http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

Basically you may get simulation issues if you use blocking assignment.

Simple testbench demonstrating how blocking and non-blocking assignment differ:

`timescale 1ns / 1ps
`default_nettype none

module verilog_uut(input wire clk, input wire i_a,
        output reg o_nb_b, output reg o_nb_c,
        output reg o_b_d, output reg o_b_e);

    always @(posedge clk) begin
        o_nb_b <= i_a;
        o_nb_c <= o_nb_b;
        
        o_b_d = i_a;
        o_b_e = o_b_d;
    end
endmodule

`default_nettype wire

`timescale 1ns / 1ps
`default_nettype none

module verilog_tb ();
    parameter CLK_PERIOD   = 20; // 50MHz
    reg          clk = 1'b0;

    reg i_a;
    wire o_nb_b, o_nb_c;
    wire o_b_d, o_b_e;

    verilog_uut verilog_uut(.clk(clk), .i_a(i_a),
            .o_nb_b(o_nb_b),    .o_nb_c(o_nb_c),
            .o_b_d(o_b_d),      .o_b_e(o_b_e));

    initial begin
        clk <= 1'b1;
        forever begin
            #(CLK_PERIOD/2);
            clk <= ~clk;
        end
    end

    initial begin: init
        i_a = 1'b0;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        
        i_a = 1'b1;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);

        i_a = 1'b0;
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        @(posedge clk);
        
        $display("Module OK");
        $finish;    
    end

endmodule

`default_nettype wire

TODO: update showing blockings vs non-blocking simulation to real mismatch

 
verilog/assignment.txt · Last modified: 2015/02/26 17:41 by mcmaster-guest
 
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