VCS considerations

This page was originally created to figure out what files should be checked in (libero 9.1) using a combination of SmartFusion and SX series devices

source/generated: indicates if its a source file or generated from tools. Generally source files should be version controlled and generated files should be archived, but not version controlled (ex: through a build server, or official builds copied to a file share). IP cores are a gray area (marked “core”): you can re-download them but Actel could vanish, change the file, etc. Some people check these in to trade stability/time for a larger repository

Obviously some files like xml and tcl are general file types that are used outside of Actel…use your best judgement, especially if you have some custom tooling

A lot of files may be “source” but have timestamps in them from being re-parsed and re-written by Libero…sucks

05/07/2014 first cut gitignores

./component/.gitignore:

!*
*~

I decided to check in anything “core like”. Thus, everything in this directly is checked in, regardless of what it is

./.gitignore:

*~
~*

*.adb
*.def
*.edn
*.fdb
*.ipd
*.loc
*.log
*.map
#*.pdb
precision.log
#*.pro
*.psp
*.rpt
# *.spi
*.srr
*.stp
_syn.prj
*.tcl
*.xml
*.vec

*.lok
*.tmp
*.exe
*.ini
.recordref*
*.areasrr
*.fse
*.htm
*.sdf
*.so
*.srd
*.srl
*.srm
*.srs
*.szr
*.tlg
*.afm
dm
run_options.txt
scratchproject.prs
synlog
syntmp
traplog.tlg
viewdraw
*FlashPro_*.L*
*.depends
*.plk
*.sav
projectData
*.srr_Min

NOTE: check in an initial adb using –force (see below for details). Then do this:

git update-index --assume-unchanged path/to/my.adb

Then manually push updates as required

Some of these files are, strictly speaking, generated. However, I checked them in to get around various issues. For example, if you don't check in the .adb file, it will prompt you to re-setup every time (part/package etc) even though it really only needs the .ide_des file. This is unfortunate sine the .adb file is is of non-trivial size.

Other notes:

  • Libero liberally distributes local system paths and timestamps into versioned files. Expect unrelated churn as you need to check in files
    • Mitigation: put files at a recommended location (eg: C:\hdl\my_project)
  • I treated my SmartGen'd Root.vhd like an IP core (checked it in): not having it checked in made Libero angry
  • Root_syn.prj can use relative paths but seems that they randomly get wiped out into absolute paths
    • Some options exist to use relative paths…still experimenting

adb

“Actel Designer database, stores the compiled design for P&R”

Source/generated: generated

Format: CFBF. Haven't tried extracting

afm

Anti-fuse FPGA programming file (ex: for SX)

bfm

Description:

Format:

Source/generated: source?

“Bus Functional Model script which you write in their ad-hoc language, compile into a .vec file, which is read and executed by a testbench instantiating their VHDL BFM models.”

“BFM is a stimulus file. These files are provide to Simulation tool.”

Stack exchange page indicates this is source but my files clearly say “Created by Actel SmartDesign”. Does SmartDesign parse this or does it generate it from another file?

cfg

“captures information about the settings that were specified for the system. ”

Source/generated: generated?

cxf

Stores design block information (ex: port definitions). Think it includes the design itself (proprietary version of EDIF?)

XML

Created by:

  • Design block flow
  • SmartGen

“Libero 8.0 introduces SmartDesign…However, SmartDesign requires a port description for the blocks it is using.”

“SmartDesign core configuration file. This and the matching .sdb allow SmartDesign to recreate the DirectCore components via its “Generate Design” command. ”

Source/generated: generated?

dat

Source/generated: generated?

“JTAG programming. Also SPI Slave Programming”

def

“Discontinued Programming file. Output file from flashpoint.”

Source/generated: generated

edn

Source/generated: generated

EDIF netlist. This is an industry standard netlist format not specific to Synopysis/Actel

fdb

“fabric programming” file. Generated by Designer's “FlashPro Data File” button

Source/generated: generated

gen

Output netlist file from the generated cores

Source/generated: core

ipd

“JTAG programming. Also SPI Slave Programming”

Source/generated: generated?

loc

Source/generated: generated?

log

“log file from configured generated cores”

Source/generated: generated

map

“lets you know the location of the Logic inside the FPGA”

Source/generated: generated

pdb

1 of 2 formats FlashPro accepts

“Actel Designer physical database; essentially the finished bitfile readable by FlashPro ”

Source/generated: generated

pdc

looks like physical design constraints. ASCII text

“Source file - keep under version control. Constraints such as pinout, I/O standards.”

Source/generated: source

precision.log

“Precision logfile”

Source/generated: generated

prj

“Project file; stores Libero settings for a project”

Source/generated: source

pro

“FlashPro settings. Generated by FlashPro. ”

psp

“Precision project file”

Source/generated: generated?

rpt

“Report. Optionally generated from a menu item in Designer. ”

Source/generated: generated

sdb

binary

Source/generated: source

“Archive to permit recreation of DirectCore components.”

sdc

Source/generated: core/depends

“Constraints generated by the tools (e.g. Synplicity). If I modify this I treat it as as source file.”

sdprj

Looks related to MSS…maybe used if you are compiling C code into SF?

spi

“Auto Programming, also Cortex-M3 ISP, and In Application Programming (IAP)”

srr

“Synplify logfile”

Source/generated: generated

stp

1 of 2 formats FlashPro accepts. STAPL is an (open?) protocol for JTAG programming

“JTAG programming. Also SPI Slave Programming”

_syn.prj

“Synplify log file”

Source/generated: generated

tcl

“Used to run synthesis”

Source/generated: generated?/depends

xml

“XML files. Some are part of the auto-generated SmartDesign, passing info to the embedded software tools. There may be others.”

Source/generated: generated?/depends

vec

“Compiled from .bfm”

Source/generated: generated

References

 
actel/files.txt · Last modified: 2014/05/13 15:31 by mcmaster-guest
 
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