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vendor:yamaha:opl2 [2019/04/07 21:49] lord_nightmare add link to D0/D1 debug info |
vendor:yamaha:opl2 [2019/12/23 12:26] lord_nightmare fix test register notes, and add note about the "dac test" |
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=== YM2413 Instruments === | === YM2413 Instruments === | ||
There is at present no die image of YM2413. In the near future, [[https:// | There is at present no die image of YM2413. In the near future, [[https:// | ||
- | === YM2413 | + | |
+ | === YM2413 | ||
+ | from Nuke.YKT' | ||
< | < | ||
- | TEST (0x0F) | + | YM2413 test data output format(!!not verified on hardware!!). |
- | 76543210 | + | /CS = 0 |
- | |||||||\- DAC test enable (enables DAC output from the top 4 bits of address 0x10 (0x10 is normally the frequency LSB bits for channel | + | /WE = 1 |
- | ||||||\-- ? | + | A0 = 0 |
- | |||||\--- ? | + | D0 and D1 serially output |
- | ||||\---- This bit, if set, silences the FM sound output. How exactly is unknown. (On YM2151 this bit freezes the phase counters and lfo counters) | + | Internal clock rate is MCLK/4 |
- | |||\----- ? | + | Clock 0 |
- | ||\------ ? | + | D0: P8 P7 P6 P5 P4 P3 P2 P1 P0 E6 E5 E4 E2 E1 E0 0 0 0 |
- | |\------- ? | + | D1: C8 C7 C6 C5 C4 C3 C2 C1 C0 0 0 0 0 0 0 0 0 0 |
- | \-------- ? | + | |
+ | Px - Operator 0 phase generator | ||
+ | Ex - Operator 17 envelope generator output | ||
+ | Cx - Channel 6(?) output | ||
</ | </ | ||
- | === YM2413 D0/D1 debug state === | ||
- | see Nuke.YKT' | ||
- | === VRC7 TEST register (0x0F) === | + | === YM2413 and VRC7 TEST register (0x0F) === |
< | < | ||
TEST (0x0F) | TEST (0x0F) | ||
76543210 | 76543210 | ||
- | |||||||\- if 1, Disables Car/Mod EG units, EG output is forced to 0 (max volume) | + | |||||||\- if 1, Disables Car/Mod EG units, EG output is forced to 0 (max volume). This can be used as a crude DAC test, see below. |
||||||\-- if 1, resets (and holds, while active) the Trem and Vib LFO counts to 0 | ||||||\-- if 1, resets (and holds, while active) the Trem and Vib LFO counts to 0 | ||
|||||\--- if 1, resets (and holds, while active) the PG count for Car/Mod at 0 (this effectively silences the chip) | |||||\--- if 1, resets (and holds, while active) the PG count for Car/Mod at 0 (this effectively silences the chip) | ||
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</ | </ | ||
+ | If bit 0 is set, this can be combined with setting bit 2, and writing the ' | ||
=== VRC7 Debug Mode === | === VRC7 Debug Mode === |