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--- tech:180nm [2014/01/02 06:41]
azonenberg
+++ tech:180nm [2015/01/04 22:50] (current)
@@ Line 1: / Line 1: @@
 nm technology node
-Example design rules for Intel 180 nm: http://ece.iisc.ernet.in/~navakant/nano/2012/180nm.pdf
+Example design rules for Intel 180 nm: http://www.clarkson.edu/~khondker/EE447_lecture6.ppt
 Devices:
 {{topic>tech_180nm}}

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--- sidebar [2024/04/22 04:35]
azonenberg
+++ sidebar [2024/04/22 04:36] (current)
azonenberg old revision restored (2022/05/21 00:28)
@@ Line 1: / Line 1: @@
-{{tag>collection_az year_unknown vendor_microchip vendor_micrel type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet foundry_tsmc tech_65nm}}
+[[:start|Top level]]
-Tech node info comes from IBIS file "[Source]      Made by TSMC 65nm IBIS model file"
+Lists of devices
-http://ww1.microchip.com/downloads/en/DeviceDoc/ksz9031%20IBIS.zip
-TODO: actually decap one :){{https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.thumb.jpg}}
+    *  [[:collection|Collection]]
+      * See for copyright info
+    * [[:foundry:start|Foundry]]
+    * [[:tech:start|Process technology]]
+    * [[:type|Type]]
+    * [[:vendor:start|Vendor]]
+    * [[:year|Year]]
-[[https://siliconpr0n.org/map/micrel/ksz9031rnx/azonenberg_mz_mit20x/|mz_mit20x]]
+For newcomers
-  * [[https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.jpg|Single]] (12317x8766, 24.8946MiB)
+    * [[:navigation|Navigating the site]]
+    * [[:your_first_page|Writing your first page]]
+Other
+    * [[:conventions|Conventions]] for naming etc
+    * [[:digitized|List of digitized chips]]
+    * [[:Counterfeit]]
+    * [[:true_mask_art|True mask art]]
+    * [[:Package|Package]]
+    * [[:stdcell|Cell libaries]]
+    * [[:hdl|HDL]]
+    * [[:prog:start|Programming]]
+    * [[:TODO|TODO]]
+    * [[:Links]]

tech/180nm.1388644895.txt.gz · Last modified: 2014/01/02 06:41 by azonenberg

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