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motorola:68000 [2013/10/05 16:45] sarayan [Die shots] |
motorola:68000 [2020/04/05 03:24] (current) mcmaster |
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| + | FIXME: think data got moved here? https:// | ||
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| ====== Die shots ====== | ====== Die shots ====== | ||
| * [[http:// | * [[http:// | ||
| - | * [[http:// | + | * [[http:// |
| * [[http:// | * [[http:// | ||
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| ====== Vectorized layers ====== | ====== Vectorized layers ====== | ||
| - | * [[http:// | + | * [[http:// |
| The svg uses m68000-m-3.png as background, which should be in the same directory. | The svg uses m68000-m-3.png as background, which should be in the same directory. | ||
| Line 16: | Line 18: | ||
| Metal layer was done by Quietust, everything else by me, Olivier Galibert. | Metal layer was done by Quietust, everything else by me, Olivier Galibert. | ||
| + | |||
| + | ====== Analysis ====== | ||
| + | * [[http:// | ||
| + | |||
| + | generate-bitmask-images generate six pbm (bitmap) images (one per layer) using librsvg for the rendering (27M each) | ||
| + | |||
| + | generate-circuit generates the mosfets, the capas, the circuits, etc from the bitmaps. | ||
| + | |||
| + | * [[http:// | ||
| + | |||
| + | The m68000.txt is a columns-based text file, with the number of entries and the block name at the start of each block. Blocks and columns are: | ||
| + | * circuits (basic elements seen on the die) | ||
| + | * circuit id | ||
| + | * circuit type (a=active, p=poly, m=metal, b=buried, t=transistor gate, c=capacitor) | ||
| + | * net id of which the circuit is part of, net id of the active layer for capas | ||
| + | * net id of the poly layer for capas, -1 for everything else | ||
| + | * x0, y0, x1, y1 coordinates of the bounding rectangle of the circuit, y=0 at bottom (as in inkscape) | ||
| + | * surface of the circuit in pixels | ||
| + | * list of neighbouring (touching) circuits, under the form < | ||
| + | * nets (groups circuits electrically linked together) | ||
| + | * net id | ||
| + | * list of circuits ids (without the types) | ||
| + | * transistors | ||
| + | * transistor id | ||
| + | * circuit id of the gate | ||
| + | * x position of the " | ||
| + | * y position of the " | ||
| + | * net id of one terminal | ||
| + | * net id of the gate | ||
| + | * net id of the other terminal | ||
| + | * length/ | ||
| + | |||
| + | ====== Visualisation ====== | ||
| + | |||
| + | * [[http:// | ||
| + | * [[http:// | ||
| + | * [[http:// | ||
| + | |||
| + | Note that the simulation program is essentially digital, with the side effect that relatively important things like the clock do not work. | ||
| + | |||
| + | The text version of the schematics is composed of 3 parts: | ||
| + | |||
| + | * Header: one line: size x, size y, size ratio w.r.t traced image | ||
| + | * Nodes: one line with the node count followed by one line per node. A node id is its line number, starting at 0. | ||
| + | * Node type, t=nmos enh, d=nmos depl, v=vcc, g=gnd, p=pad, c=capacitor | ||
| + | * x position | ||
| + | * y position | ||
| + | * linked nets ids (t1/gate/t2 for t/d, t for v/g/p, t1/t2 for c) | ||
| + | * w/l ratio for transistors, | ||
| + | * orientation (except for v/g) | ||
| + | * name | ||
| + | * Nets, one line with the node count followed by one line per net. A net is is its line number, starting at 0. | ||
| + | * Number of reference points in the net drawing (beware, can be 0) | ||
| + | * x, y coordinates of each point, the id of a point is its number, starting at 0 | ||
| + | * Number of lines in the net drawing (beware, can be 0) | ||
| + | * pid1, pid2 points ids of the start and end point of each line | ||
| + | * Number of big dots in the net drawing (beware, can be 0) | ||
| + | * points ids of the big dots | ||
| + | * Name of the net, often a number | ||
| + | |||
| + | ====== Schematics ====== | ||
| + | * [[http:// | ||
| + | * [[http:// | ||
| + | * [[http:// | ||
| + | * [[http:// | ||
| + | * [[http:// | ||
| + | |||
| + | The schematics are automatically generated from the previously generated files then the circuits are moved around by a lua program. | ||
| + | |||
| + | ====== Schematics analysis ====== | ||
| + | ===== Standard circuits ===== | ||
| + | ==== Latch ==== | ||
| + | |||
| + | The 68000 uses a *lot* of latches. | ||
| + | |||
| + | {{: | ||
| + | |||
| + | The latch value is set through the input line. The value goes through two inverters then loops through a weak (l/w < 0.2) enhancement mosfet with terminal and gate tied. That way the input drive can easily override it to set a new value. | ||
| + | |||
| + | Both the output and its inverse are available, making it easy to build an amplifier afterwards. | ||
| + | |||
| + | ==== Register bit ==== | ||
| + | |||
| + | The register bits are described in patent 4, | ||
| + | |||
| + | {{: | ||
| + | |||
| + | At the center two inverters are looped to keep the value. | ||
| + | |||
| + | |||
| + | ====== References ====== | ||
| + | |||
| + | * Die revs: http:// | ||
| + | * Early die revs: https:// | ||
| + | * J5H was first silicon, R9M was second | ||