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mcmaster:start [2022/05/25 16:06]
mcmaster [Table]
mcmaster:start [2023/02/16 10:17] (current)
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     * Decapping involves harsh chemicals, direct expenses, high NRE, and time so contributions are greatly appreciated     * Decapping involves harsh chemicals, direct expenses, high NRE, and time so contributions are greatly appreciated
   * Any potential legal issues associated with the chip?   * Any potential legal issues associated with the chip?
-    * Ex: DRM, crypto+    * If so, it will be evaluated on a case by case basis 
 +    * Ex: DRM, crypto can be problematic
     * Ex: a typical sound chip or microcontroller is not an issue     * Ex: a typical sound chip or microcontroller is not an issue
 +    * I will not work on: satellite, cable TV
   * Clearly identify the chips, especially if you are sending more than one   * Clearly identify the chips, especially if you are sending more than one
     * Ex: specify "344S0061-A" instead of"SWIM", since that's what's printed on it     * Ex: specify "344S0061-A" instead of"SWIM", since that's what's printed on it
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 In general I want to focus on R&D / labwork and not hand digitization.  I do have some limited semi-automatic digitization capabilities for planarized chips though that I'd like to develop (ex: works on PS1 chipset). In general I want to focus on R&D / labwork and not hand digitization.  I do have some limited semi-automatic digitization capabilities for planarized chips though that I'd like to develop (ex: works on PS1 chipset).
  
-Most of this is targeted towards small chips up to the mid 90's.  If the die is obnoxiously large (ex: 486 CPU) it will be difficult for me to photograph and stitch the entire thing.  Similarly most of my equipment is targeted towards larger processes (say 180+nm), although I do have a small SEM if required. See [[https://siliconpr0n.org/map/xilinx/xc2c32a/lap4-04_mit20x/|XC2C32A]] for an example 180 nm chip taken with a relatively low power objective, noting in theory I can get about 11x the detail (NA 0.42 => 1.4).+Most of this is targeted towards small chips up to the mid 90's.  If the die is obnoxiously large (ex: 486 CPU) it will be difficult for me to photograph and stitch the entire thing.  Similarly most of my equipment is targeted towards larger processes (say 180+nm), although I do have a small SEM if required. See [[https://siliconpr0n.org/map/xilinx/xc2c32a/mcmaster_lap4-04_mit20x/|XC2C32A]] for an example 180 nm chip taken with a relatively low power objective, noting in theory I can get about 11x the detail (NA 0.42 => 1.4).
  
 Other: most of the work is in decapping, not actual imaging. If you happen to already have a bare, clean die and would be satisfied with a quick / lower quality scan, feel free to send me a few dies. This also can work out well since most of the NRE cost is in the microscope, not the decapping supplies. Other: most of the work is in decapping, not actual imaging. If you happen to already have a bare, clean die and would be satisfied with a quick / lower quality scan, feel free to send me a few dies. This also can work out well since most of the NRE cost is in the microscope, not the decapping supplies.
 
mcmaster/start.txt · Last modified: 2023/02/16 10:17 (external edit)
 
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