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mcmaster:st:24c026 [2012/07/06 20:08] azonenberg [Detailed analysis] |
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| - | {{tag> | ||
| - | {{tag> | ||
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| - | ====== Overview ====== | ||
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| - | {{: | ||
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| - | ====== Map ====== | ||
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| - | Top metal: http:// | ||
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| - | Stripped: http:// | ||
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| - | Other stuff, just browse around http:// | ||
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| - | ====== Package ====== | ||
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| - | {{: | ||
| - | {{: | ||
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| - | ====== Nets ====== | ||
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| - | Power: | ||
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| - | ====== Sectors ====== | ||
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| - | {{: | ||
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| - | ^ Number ^ High level description ^ Claimed by ^ Digitized? ^ Transistor schematic? ^ Functional schematic? ^ Other ^ | ||
| - | | 1 | Unknown | | | | | | | ||
| - | | 2 | Unknown | | | | | | | ||
| - | | 3 | Unknown | | | | | | | ||
| - | | 4 | Unknown | | | | | | | ||
| - | | 5 | Unknown | | | | | | | ||
| - | | 6 | Unknown | | | | | | | ||
| - | | 7 | Unknown | | | | | | | ||
| - | | 8 | Unknown | | | | | | | ||
| - | | 9 | Unknown | | | | | | | ||
| - | | 10 | Unknown | | | | | | | ||
| - | | 11 | Unknown | | | | | | | ||
| - | | 12 | Unknown | | | | | | | ||
| - | | 13 | Unknown | | | | | | | ||
| - | | 14 | ROM / microcode? | | | | | | | ||
| - | | 15 | ROM / microcode? | | | | | | | ||
| - | | 16 | Unknown | | | | | | | ||
| - | | 17 | clock? | JM | Y | Y | Half | Right half to meaningful high level schematic. | ||
| - | | 18 | Unknown | | | | | | | ||
| - | | 19 | Unknown | | | | | | | ||
| - | | 20 | Unknown | | | | | | | ||
| - | | 21 | Unknown | | | | | | | ||
| - | | 22 | Unknown | | | | | | | ||
| - | | 23 | Unknown | | | | | | | ||
| - | | 24 | EEPROM | AZ | IP| | | | | ||
| - | | 25 | EEPROM row/ | ||
| - | | 26 | EEPROM row/ | ||
| - | | 27 | EEPROM row/ | ||
| - | | 28 | charge pump caps and switches | JM | Y | | | Schematic capture | | ||
| - | | 29 | charge pump supply diode? | JM | Y | | | Schematic capture | | ||
| - | | 30 | charge pump control? | JM | Y | | | Schematic capture | | ||
| - | | 31 | Unknown | | | | | | | ||
| - | | 32 | Unknown | | | | | | | ||
| - | | 33 | Unknown | | | | | | | ||
| - | | 34 | Unknown | | | | | | | ||
| - | | 35 | Unknown | | | | | | | ||
| - | | 36 | Unknown | | | | | | | ||
| - | | 37 | Unknown | | | | | | | ||
| - | | 38 | Unknown | | | | | | | ||
| - | | 39 | Unknown | | | | | | | ||
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| - | ====== Sector analysis ====== | ||
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| - | ===== 24 - EEPROM cells ===== | ||
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| - | ==== Overview ==== | ||
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| - | The entire EEPROM array (shown below) is known to be 2048 bits. | ||
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| - | {{: | ||
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| - | The array consists of a cell (shown below) tiled 16 wide by 8 high, for 128 copies of the cell. Each cell must thus be 16 bits. Each cell consists of four sub-cells, so each sub-cell is 4 bits. | ||
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| - | ==== Detailed analysis ==== | ||
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| - | This block contains four EEPROM bits, one per quadrant. | ||
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| - | The purple area is active area (doping unknown at this point). | ||
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| - | {{: | ||
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| - | Note that each cell contains two horizontal lines (the center is shared) and one vertical. | ||
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| - | To read out a bit, the column select line for this cell is asserted (active high vs low polarity unknown at this point) and the other deasserted. Suppose we're reading the two bits in the left half. | ||
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| - | {{: | ||
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| - | At this point the left half of the cell (two bits) is active and the right is inactive. Current can now flow between terminals A and B if the upper floating gate is appropriately charged (high vs low unknown at this point) and between A and C if the lower is turned on. It's not known at this point whether A is driven and B/C are sense lines, or vice versa. The first would allow two bits to be read at a time rather than one but would require twice as many sense amplifiers. | ||
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| - | It's also unknown why the floating gates have two fingers over the active area rather than a solid plate. | ||
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| - | The write cycle has not been studied yet. | ||