Differences

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--- mcmaster:st:24c026 [2012/07/06 20:08]
azonenberg [Detailed analysis]
+++ mcmaster:st:24c026 [2023/02/08 05:47]
mcmaster removed
@@ Line 1: / Line 1: @@
-{{tag>collection_jm}}
+{{tag>collection_mcmaster vendor_st year_1994 type_memory type_memory/eeprom foundry_unknown tech_unknown}}
-{{tag>vendor_st}}
-{{tag>year_1994}}
 ====== Overview ======
@@ Line 10: / Line 8: @@
 ====== Map ======
-Top metal: http://siliconpr0n.org/map/st/24c02/top_metal__ns50xu/
+Top metal: http://siliconpr0n.org/map/st/24c02/mz__ns50xu/
 Stripped: http://siliconpr0n.org/map/st/24c02/stripped__ns50xu/
@@ Line 57: / Line 55: @@
 | 22 | Unknown | | | | | |
 | 23 | Unknown | | | | | |
-| 24 | EEPROM | AZ | IP| | | |
+| 24 | EEPROM | AZ | Y | IP | |Still double-checking accuracy of tracing|
 | 25 | EEPROM row/col/data? | | | | | |
 | 26 | EEPROM row/col/data? | | | | | |
@@ Line 92: / Line 90: @@
 This block contains four EEPROM bits, one per quadrant.
-The purple area is active area (doping unknown at this point).
+The purple area is active area (doping unknown at this point). The two bars on the left and right appear to be guard rings and can be safely ignored.
 {{:mcmaster:st:24c026:eepromcells.png?500|}}
@@ Line 102: / Line 100: @@
 {{:mcmaster:st:24c026:eepromcells_read_1.png?500|}}
-At this point the left half of the cell (two bits) is active and the right is inactive. Current can now flow between terminals A and B if the upper floating gate is appropriately charged (high vs low unknown at this point) and between A and C if the lower is turned on. It's not known at this point whether A is driven and B/C are sense lines, or vice versa. The first would allow two bits to be read at a time rather than one but would require twice as many sense amplifiers.
+At this point the left half of the cell (two bits) is active and the right is inactive. Current can now flow between terminals A and B if the upper floating gate is appropriately charged (high vs low unknown at this point) and between A and C if the lower is turned on. In this example the upper left bit is a 1 and the lower left is a 0.
-It's also unknown why the floating gates have two fingers over the active area rather than a solid plate.
+It's not known at this point whether A is driven and B/C are sense lines, or vice versa. The first would allow two bits to be read at a time rather than one but would require twice as many sense amplifiers. If B were driven and A read out, then bit pair "11" would result in C going high which is probably not desirable.
+It's also unknown why the floating gates have two fingers over the active area rather than a solid plate. Possibly something to do with leakage? The big plate to the side (over the guard ring) is most likely there to increase capacitance of the floating gate.
 The write cycle has not been studied yet.
+===== References =====
+ * http://uvicrec.blogspot.com/2012/07/st-24c02-sector-17r-clock.html