Dual integrating sigma-delta ADC/DAC

NorTel CMOS41S process, 1.2 micron, double metal, double poly
spec'ed clock rate is 10.24 MHz
funtion is to test a double integration sigma delta modulated ADC and DAC
analog switched capacitor filters on front end
digital logic does decimation on ADC path and interpolation on DAC path

Package





Die



mz_mit20x

  • Single (21661×13629, 78.08MB)
 
mcmaster/northern-telecom/t36a.txt · Last modified: 2019/07/04 21:53 by mcmaster
 
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