[[azonenberg:nvidia:mcpx]]
 
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azonenberg:nvidia:mcpx [2014/03/09 20:19]
azonenberg [Die] 		azonenberg:nvidia:mcpx [2015/01/04 22:50] (current)
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   * M5 = medium-range vertical interconnect   * M5 = medium-range vertical interconnect
   * M4 = medium-range horizontal interconnect   * M4 = medium-range horizontal interconnect
-  * M3 = short-range horizontal interconnect +  * M3 = short-range vertical interconnect 
-  * M2 = short-range vertical interconnect+  * M2 = short-range horizontal interconnect
   * M1 = intra-cell routing   * M1 = intra-cell routing
  
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 {{:azonenberg:nvidia:mcpx_21_bf_neo20x_annotated.jpg?600|}} {{:azonenberg:nvidia:mcpx_21_bf_neo20x_annotated.jpg?600|}}
  
-Mask rev markings. Looks very similar to the [[http://siliconpr0n.org/wiki/doku.php?id=mcmaster:nvidia:geforce_2_mx|GeForce 2 MX]] suggesting the two are made on the same, or nearly same, process. This is a little odd since the GeForce 2 was supposed to be 180 nm and sources list this chip as 150.+Mask rev markings. Looks very similar to the [[mcmaster:nvidia:geforce_2_mx|GeForce 2 MX]] suggesting the two are made on the same, or nearly same, process. This is a little odd since the GeForce 2 was supposed to be 180 nm and sources list this chip as 150.
  
 {{:azonenberg:nvidia:mcpx_22_bf_neo20x_annotated.jpg?600|}} {{:azonenberg:nvidia:mcpx_22_bf_neo20x_annotated.jpg?600|}}
 
azonenberg/nvidia/mcpx.1394396354.txt.gz · Last modified: 2014/03/09 20:19 by azonenberg
 
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