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| - | Myricom PCI DMA ASIC from a 2gbps Myrinet NIC found by John McMaster in the MIT tech dump. | ||
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| - | We also decapped the [[xbar|crossbar switch ASIC]] from the switch in the same cluster. | ||
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| - | Has a Taz and a butterfly on it. | ||
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| - | ====== Board ====== | ||
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| - | From Amazon listing but the chip is labeled " | ||
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| - | ====== Die shots ====== | ||
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| - | Die label. Quick focus stack of two images. | ||
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| - | Overview. Device is a 3-metal process but has classical 2-metal design (standard cells with 7 horizontal routing tracks between them on M1, then vertical routing on M2). M3 is used for long-haul power routing and what appears to be a low-skew clock distribution grid. | ||
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| - | Huge amounts of wasted space (multiple blank areas with no routing or logic, each several hundred microns square). The die could probably have been made quite a bit smaller if anyone bothered to try... maybe it was faster this way? | ||
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| - | Original measurements overestimated the feature size, it now looks to be around 350nm technology. | ||
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| - | Close up of random cell area. | ||
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| - | Large data bus with clock grid over it (even though there' | ||
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| - | SRAM block, looks like some kind of packet buffer. | ||
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| - | ====== Art ====== | ||
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