Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Next revision
Previous revision
azonenberg:microchip:pic32mx340f512h [2014/03/23 04:13]
azonenberg created
azonenberg:microchip:pic32mx340f512h [2015/01/04 22:50] (current)
Line 1: Line 1:
-{{tag>collection_az vendor_microchip type_processor type_processor/microcontroller type_processor/microcontroller/pic type_processor/microcontroller/mips year_unknown foundry_unknown tech_unknown}}+{{tag>collection_az vendor_microchip type_processor type_processor/microcontroller type_processor/microcontroller/pic type_processor/microcontroller/mips year_unknown foundry_tsmc tech_180nm}}
  
-Microchip PIC32 microcontroller.+Microchip PIC32 microcontroller. Made on TSMC 180nm according to change notices, but measurements of channel length show closer to 250.
  
-* 32 KB of SRAM +  * 32 KB of SRAM 
-* 512 KB of NOR flash +  * 512 KB of NOR flash 
-* MIPS M4K CPU +  * MIPS M4K CPU 
-* ADC +  * ADC 
-* PLL +  * PLL 
-* Other miscellaneous stuff+  * Other miscellaneous stuff 
 + 
 +IBIS model: Package made by Amkor. 
 + 
 +[[http://www.microchip.com/mymicrochip/NotificationDetails.aspx?pcn=CYER-29IERZ854&opennew=n|YPAA1 Rev B2 EMB Flash HE 1K Process Qualification Report]] 
 + 
 +Can be made at one of several fabs. One of these is TSMC Fab 11, MSL 548, EMB FLASH 1K process.
  
 ====== Package ====== ====== Package ======
Line 26: Line 32:
 Size is approximately 4280 x 4740 μm (20.29 mm<sup>2</sup>). Size is approximately 4280 x 4740 μm (20.29 mm<sup>2</sup>).
  
-Looks to be a 4-metal ~220 nm process.+Looks to be a 4-metal 250 nm process.
  
 ===== M4 (top layer) ===== ===== M4 (top layer) =====
Line 65: Line 71:
 Overview Overview
  
-{{:azonenberg:microchip:pic32mx340f512h_m1_bf_neo5x_4k.jpg?600|}}+{{:azonenberg:microchip:pic32mx340f512h_m1_bf_neo5x_4k.jpg?1000|}}
  
 Top left corner of SRAM array Top left corner of SRAM array
Line 78: Line 84:
  
 {{:azonenberg:microchip:pic32mx340f512h_36_bf_neo40x_annotated.jpg?600|}} {{:azonenberg:microchip:pic32mx340f512h_36_bf_neo40x_annotated.jpg?600|}}
 +
 +===== Active =====
 +
 +NOR flash
 +
 +{{:azonenberg:microchip:pic32mx340f512h_01_se_9000x_15kv_15mm.jpg?600|}}
 +
 +{{:azonenberg:microchip:pic32mx340f512h_02_se_35kx_15kv_15mm.jpg?600|}}
 +
 +6T SRAM
 +
 +{{:azonenberg:microchip:pic32mx340f512h_04_se_4500x_15kv_15mm.jpg?600|}}
 +
 +{{:azonenberg:microchip:pic32mx340f512h_05_se_15kx_15kv_15mm.jpg?600|}}
 +
 +Random logic. 250 nm channel length.
 +
 +{{:azonenberg:microchip:pic32mx340f512h_06_se_5kx_5kv_15mm.jpg?600|}}
 +
 +{{:azonenberg:microchip:pic32mx340f512h_07_se_18kx_5kv_15mm.jpg?600|}}
 +
 
azonenberg/microchip/pic32mx340f512h.1395548014.txt.gz · Last modified: 2014/03/23 04:13 by azonenberg
 
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution 4.0 International
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki