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azonenberg:microchip:pic32mx340f512h [2014/03/23 04:14] azonenberg |
azonenberg:microchip:pic32mx340f512h [2015/01/04 22:50] |
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- | Microchip PIC32 microcontroller. | ||
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- | * 32 KB of SRAM | ||
- | * 512 KB of NOR flash | ||
- | * MIPS M4K CPU | ||
- | * ADC | ||
- | * PLL | ||
- | * Other miscellaneous stuff | ||
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- | ====== Package ====== | ||
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- | Markings: | ||
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- | (Microchip logo) | ||
- | PIC32MX340F | ||
- | 512H-80I/MR | ||
- | (e3) | ||
- | 0850KGV | ||
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- | ====== Die ====== | ||
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- | Size is approximately 4280 x 4740 μm (20.29 mm< | ||
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- | Looks to be a 4-metal ~220 nm process. | ||
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- | ===== M4 (top layer) ===== | ||
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- | Overview | ||
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- | Interesting region in the middle of the die. Not sure what it does but provides a nice view of standard cells on lower layers. | ||
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- | Test points on the flash array. Probably tied to bit/word lines. Maybe used for measuring read/erase margins during characterization? | ||
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- | Random wiring in the middle of the die with test points | ||
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- | Mask rev markings | ||
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- | Test patterns on bottom edge | ||
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- | ===== Delayering (HF) ===== | ||
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- | Power busing near flash with exposed vias. ~700 nm via pitch is consistent with the 220-250 nm process node. | ||
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- | ===== M1 ===== | ||
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- | Overview | ||
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- | Top left corner of SRAM array | ||
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- | Edge of flash array | ||
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- | Random standard cell region. Note large number of dummy cells. This is most likely due to their use of a cost-optimized process with less metal layers than would be necessary to route the design with more densely packed cells. | ||
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