Differences

This shows you the differences between two versions of the page.

--- azonenberg:microchip:pic12f683 [2014/03/14 00:18]
azonenberg
+++ azonenberg:microchip:pic12f683 [2023/02/17 06:08] (current)
mcmaster
@@ Line 3: / Line 3: @@
 Microchip PIC12F683.
-[[http://siliconpr0n.org/map/microchip/pic12f683/top_metal_am40x/|Map (am40x, some stitching artifacts)]]
+[[http://siliconpr0n.org/map/microchip/pic12f683/azonenberg_mz_am40x/|Map (am40x, some stitching artifacts)]]
 ====== Package ======
@@ Line 11: / Line 11: @@
 ====== Metal 3 ======
-{{:azonenberg:microchip:pic12f683_m3_bf_neo10x_small.jpg?600|}}
+Size is approximately 2020 x 2240 μm (4.52 mm<sup>2</sup>)
+{{:azonenberg:microchip:pic12f683_m3_bf_neo10x_4k.jpg?600|}}
 ===== Logo =====
@@ Line 65: / Line 67: @@
 {{:azonenberg:microchip:pic12f683_poly_bf_neo10x_4k.jpg?600|}}
+===== EEPROM =====
+{{:azonenberg:microchip:pic12f683_poly_03_bf_neo40x_annotated.jpg?300|}} {{:azonenberg:microchip:pic12f683_poly_06_bf_neo40x_annotated.jpg?300|}}
+===== SRAM =====
+{{:azonenberg:microchip:pic12f683_poly_01_bf_neo40x_annotated.jpg?300|}}
+T cell size is 5.25 μm x 7.35 μm (38.6 μm^2).
+===== Flash =====
+{{:azonenberg:microchip:pic12f683_poly_05_bf_neo40x_annotated.jpg?300|}}
+===== Fuses =====
+{{:azonenberg:microchip:pic12f683_poly_04_bf_neo40x_annotated.jpg?300|}}
+===== Random logic =====
+{{:azonenberg:microchip:pic12f683_poly_02_bf_neo40x_annotated.jpg?300|}}
+===== Random notes =====
+Flash
++ 32 horizontal = 56 on bottom x 32 on side = 1792 unit cells
+	Actual flash capacity is 2048 14-bit words = 28672 bits so each unit cell = 16 bits. 4x4?
+SRAM
+columns of 8 bits each
+rows
+	Horizontal WLs
+	Vertical BLs
+bit row address bus
+bit col address bus
+EEPROM
+bytes
+horizontal x 16 vertical = 256 unit cells
+	Seems to be some dummy bits?

--- sidebar [2024/04/22 04:35]
azonenberg
+++ sidebar [2024/04/22 04:36] (current)
azonenberg old revision restored (2022/05/21 00:28)
@@ Line 1: / Line 1: @@
-{{tag>collection_az year_unknown vendor_microchip vendor_micrel type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet foundry_tsmc tech_65nm}}
+[[:start|Top level]]
-Tech node info comes from IBIS file "[Source]      Made by TSMC 65nm IBIS model file"
+Lists of devices
-http://ww1.microchip.com/downloads/en/DeviceDoc/ksz9031%20IBIS.zip
-TODO: actually decap one :){{https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.thumb.jpg}}
+    *  [[:collection|Collection]]
+      * See for copyright info
+    * [[:foundry:start|Foundry]]
+    * [[:tech:start|Process technology]]
+    * [[:type|Type]]
+    * [[:vendor:start|Vendor]]
+    * [[:year|Year]]
-[[https://siliconpr0n.org/map/micrel/ksz9031rnx/azonenberg_mz_mit20x/|mz_mit20x]]
+For newcomers
-  * [[https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.jpg|Single]] (12317x8766, 24.8946MiB)
+    * [[:navigation|Navigating the site]]
+    * [[:your_first_page|Writing your first page]]
+Other
+    * [[:conventions|Conventions]] for naming etc
+    * [[:digitized|List of digitized chips]]
+    * [[:Counterfeit]]
+    * [[:true_mask_art|True mask art]]
+    * [[:Package|Package]]
+    * [[:stdcell|Cell libaries]]
+    * [[:hdl|HDL]]
+    * [[:prog:start|Programming]]
+    * [[:TODO|TODO]]
+    * [[:Links]]