Differences

This shows you the differences between two versions of the page.

--- azonenberg:cypress:cy8c4245axi [2014/08/24 19:49]
azonenberg [Active area]
+++ azonenberg:cypress:cy8c4245axi [2015/01/04 22:50] (current)
@@ Line 1: / Line 1: @@
-{{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_130nm}}
+{{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_130nm foundry_cypress}}
-PSoC 4200 series device.
+PSoC 4200 series device originally made on Cypress's [[http://www.cypress.com/?docID=45736|S8 SONOS process]] in the Minnesota fab (Fab 4, S8DIN-5R). GSMC in China has also licensed the S8 process technology; traceability markings presumably tell where the device came from but this isn't known yet.
   * Cortex-M0 CPU at up to 48 MHz
@@ Line 13: / Line 13: @@
 Looks like >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending.
+====== Stackup from change notice 145273 (TODO: Measure against actual die) ======
+Ti/AlCu/TiW to Ti/TiN/AlCu/Ti/TiN for metallization in fab 4 (except for top layers)
+  * Metal 1: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN
+  * Metal 2: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN
+  * Metal 3: 500A TiW/21,250A Al 0.5% Cu/300A TiW
+Passivation: 1000A TEOS/9000A Si3N4
+Gate stack: SiO2 / 110A & SiO2 / 32A
 ====== Package ======

--- sidebar [2024/04/22 04:35]
azonenberg
+++ sidebar [2024/04/22 04:36] (current)
azonenberg old revision restored (2022/05/21 00:28)
@@ Line 1: / Line 1: @@
-{{tag>collection_az year_unknown vendor_microchip vendor_micrel type_interface type_interface/serdes type_interface/serdes/ethernet type_network type_network/ethernet foundry_tsmc tech_65nm}}
+[[:start|Top level]]
-Tech node info comes from IBIS file "[Source]      Made by TSMC 65nm IBIS model file"
+Lists of devices
-http://ww1.microchip.com/downloads/en/DeviceDoc/ksz9031%20IBIS.zip
-TODO: actually decap one :){{https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.thumb.jpg}}
+    *  [[:collection|Collection]]
+      * See for copyright info
+    * [[:foundry:start|Foundry]]
+    * [[:tech:start|Process technology]]
+    * [[:type|Type]]
+    * [[:vendor:start|Vendor]]
+    * [[:year|Year]]
-[[https://siliconpr0n.org/map/micrel/ksz9031rnx/azonenberg_mz_mit20x/|mz_mit20x]]
+For newcomers
-  * [[https://siliconpr0n.org/map/micrel/ksz9031rnx/single/micrel_ksz9031rnx_azonenberg_mz_mit20x.jpg|Single]] (12317x8766, 24.8946MiB)
+    * [[:navigation|Navigating the site]]
+    * [[:your_first_page|Writing your first page]]
+Other
+    * [[:conventions|Conventions]] for naming etc
+    * [[:digitized|List of digitized chips]]
+    * [[:Counterfeit]]
+    * [[:true_mask_art|True mask art]]
+    * [[:Package|Package]]
+    * [[:stdcell|Cell libaries]]
+    * [[:hdl|HDL]]
+    * [[:prog:start|Programming]]
+    * [[:TODO|TODO]]
+    * [[:Links]]