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azonenberg:cypress:cy8c4245axi [2014/08/23 21:38]
azonenberg |
azonenberg:cypress:cy8c4245axi [2015/01/04 22:50] (current)
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| {{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_130nm}} | {{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_130nm foundry_cypress}} |
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| PSoC 4200 series device. | PSoC 4200 series device originally made on Cypress's [[http://www.cypress.com/?docID=45736|S8 SONOS process]] in the Minnesota fab (Fab 4, S8DIN-5R). GSMC in China has also licensed the S8 process technology; traceability markings presumably tell where the device came from but this isn't known yet. |
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| * Cortex-M0 CPU at up to 48 MHz | * Cortex-M0 CPU at up to 48 MHz |
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| Looks like >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending. | Looks like >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending. |
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| | ====== Stackup from change notice 145273 (TODO: Measure against actual die) ====== |
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| | Ti/AlCu/TiW to Ti/TiN/AlCu/Ti/TiN for metallization in fab 4 (except for top layers) |
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| | * Metal 1: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN |
| | * Metal 2: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN |
| | * Metal 3: 500A TiW/21,250A Al 0.5% Cu/300A TiW |
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| | Passivation: 1000A TEOS/9000A Si3N4 |
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| | Gate stack: SiO2 / 110A & SiO2 / 32A |
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| ====== Package ====== | ====== Package ====== |
| {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_20_bf_neo40x_annotated.jpg?600|}} | {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_20_bf_neo40x_annotated.jpg?600|}} |
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| NOR Flash | NOR Flash. Interesting structure, haven't seen this before. |
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| {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_21_bf_neo40x_annotated.jpg?600|}} | {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_21_bf_neo40x_annotated.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_01.jpg?600|}} |
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| Random logic | Random logic |
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| {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_22_bf_neo40x_annotated.jpg?600|}} | {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_22_bf_neo40x_annotated.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_02.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_03.jpg?600|}} |
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| Mysterious small SRAM blocks... FIFOs? | Mysterious small SRAM blocks... FIFOs? |
| {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_23_bf_neo40x_annotated.jpg?600|}} | {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_23_bf_neo40x_annotated.jpg?600|}} |
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| Portion of the UDB | UDB area |
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| {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_03_bf_neo40x_annotated.jpg?600|}} | {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_03_bf_neo40x_annotated.jpg?600|}} |
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| SRAM block | {{:azonenberg:cypress:cy8c4245axi:psoc4_07.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_08.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_09.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_10.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_11.jpg?600|}} |
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| | SRAM block. Single port 6T cells. |
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| {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_04_bf_neo40x_annotated.jpg?600|}} | {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_04_bf_neo40x_annotated.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_05.jpg?600|}} |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_06.jpg?600|}} |
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| | Analog block. Comparator? |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_13.jpg?600|}} |
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| | More random memory. Looks like a different 6T cell, possibly another IP library? |
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| | {{:azonenberg:cypress:cy8c4245axi:psoc4_14.jpg?600|}} |
