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azonenberg:cypress:cy8c4245axi [2014/08/05 05:05] azonenberg |
azonenberg:cypress:cy8c4245axi [2015/01/04 22:50] (current) |
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- | {{tag> | + | {{tag> |
- | PSoC 4200 series device. | + | PSoC 4200 series device |
* Cortex-M0 CPU at up to 48 MHz | * Cortex-M0 CPU at up to 48 MHz | ||
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* 4 Universal Digital Blocks (UDBs, basically CPLD function blocks) | * 4 Universal Digital Blocks (UDBs, basically CPLD function blocks) | ||
- | Looks like 130 nm or smaller tech with >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending. | + | Confirmed by SEM imaging to be 130nm tech, layer count not measured. |
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+ | Looks like >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending. | ||
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+ | ====== Stackup from change notice 145273 (TODO: Measure against actual die) ====== | ||
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+ | Ti/AlCu/TiW to Ti/ | ||
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+ | * Metal 1: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN | ||
+ | * Metal 2: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN | ||
+ | * Metal 3: 500A TiW/21,250A Al 0.5% Cu/300A TiW | ||
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+ | Passivation: | ||
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+ | Gate stack: SiO2 / 110A & SiO2 / 32A | ||
====== Package ====== | ====== Package ====== | ||
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- | NOR Flash | + | NOR Flash. Interesting structure, haven' |
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Random logic | Random logic | ||
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Mysterious small SRAM blocks... FIFOs? | Mysterious small SRAM blocks... FIFOs? | ||
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- | Portion of the UDB | + | UDB area |
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- | SRAM block | + | {{: |
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+ | SRAM block. Single port 6T cells. | ||
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+ | Analog block. Comparator? | ||
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+ | More random memory. Looks like a different 6T cell, possibly another IP library? | ||
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+ | {{: |