This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision | ||
azonenberg:cypress:cy8c4245axi [2014/06/11 03:23] azonenberg |
azonenberg:cypress:cy8c4245axi [2015/01/04 22:50] (current) |
||
---|---|---|---|
Line 1: | Line 1: | ||
- | {{tag> | + | {{tag> |
- | PSoC 4200 series device. | + | PSoC 4200 series device |
* Cortex-M0 CPU at up to 48 MHz | * Cortex-M0 CPU at up to 48 MHz | ||
Line 10: | Line 10: | ||
* 4 Universal Digital Blocks (UDBs, basically CPLD function blocks) | * 4 Universal Digital Blocks (UDBs, basically CPLD function blocks) | ||
- | Looks like around 130 nm tech with 4+ layers. | + | Confirmed by SEM imaging to be 130nm tech, layer count not measured. |
+ | |||
+ | Looks like >= 4 metal layers | ||
+ | |||
+ | ====== Stackup from change notice 145273 (TODO: Measure against actual die) ====== | ||
+ | |||
+ | Ti/AlCu/TiW to Ti/ | ||
+ | |||
+ | * Metal 1: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN | ||
+ | * Metal 2: 150A Ti/250A TiN/3200A Al 0.5% Cu/90A Ti/500A TiN | ||
+ | * Metal 3: 500A TiW/21,250A Al 0.5% Cu/300A TiW | ||
+ | |||
+ | Passivation: | ||
+ | |||
+ | Gate stack: SiO2 / 110A & SiO2 / 32A | ||
====== Package ====== | ====== Package ====== | ||
Line 26: | Line 40: | ||
====== Die ====== | ====== Die ====== | ||
+ | |||
+ | ===== Top metal ===== | ||
Size is approximately 2120 x 3210 μm (6.80 mm< | Size is approximately 2120 x 3210 μm (6.80 mm< | ||
- | Overview | + | Die overview. Bond pads are mostly grouped into blocks of 9, most likely one ground and eight I/O. The isolated ones in the upper right are probably power, the four at bottom left are probably port 4 since it only has four pins and lacks an associated ground. A full pinout could likely be recovered fairly easily by going clockwise from this block. |
{{: | {{: | ||
Line 37: | Line 53: | ||
{{: | {{: | ||
- | Random vertical interconnect routing on top metal. Smallest observed top metal half-pitch is 1.6 μm (1.7 μm wire, 1.5 μm space). This is very coarse compared to the lower metal layers... either this is a deep-submicron process with thick top metal, or they just want low resistance on the top layer for long-range routing of analog signals with minimal losses. | + | Random vertical interconnect routing on top metal. Smallest observed top metal half-pitch is 1.6 μm (1.7 μm wire, 1.5 μm space). This is very coarse compared to the lower metal layers... either this is a deep-submicron process with thick top metal for power, or they just want low resistance on the top layer for long-range routing of analog signals with minimal losses. |
{{: | {{: | ||
Line 49: | Line 65: | ||
Same region of die with focal plane on Mtop-2. | Same region of die with focal plane on Mtop-2. | ||
- | {{: | + | {{: |
+ | |||
+ | ===== Active area ===== | ||
+ | |||
+ | {{: | ||
+ | |||
+ | Boot ROM | ||
+ | |||
+ | {{: | ||
+ | |||
+ | I/O cell | ||
+ | |||
+ | {{: | ||
+ | |||
+ | NOR Flash. Interesting structure, haven' | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | Random logic | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | Mysterious small SRAM blocks... FIFOs? | ||
+ | |||
+ | {{: | ||
+ | |||
+ | UDB area | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | SRAM block. Single port 6T cells. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | Analog block. Comparator? | ||
+ | |||
+ | {{: | ||
+ | |||
+ | More random memory. Looks like a different 6T cell, possibly another IP library? | ||
+ | |||
+ | {{: |