Differences

This shows you the differences between two versions of the page.

--- azonenberg:cypress:cy8c4245axi [2014/06/11 03:32]
azonenberg
+++ azonenberg:cypress:cy8c4245axi [2014/09/28 04:21]
azonenberg
@@ Line 1: / Line 1: @@
-{{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_unknown}}
+{{tag>collection_az vendor_cypress year_2012 type_analog type_soc type_processor type_processor/microcontroller type_processor/microcontroller/arm type_processor/microcontroller/arm/cortex_m0 tech_130nm foundry_cypress}}
-PSoC 4200 series device.
+PSoC 4200 series device originally made on Cypress's [[http://www.cypress.com/?docID=45736|S8 SONOS process]] in the Minnesota fab. GSMC in China has also licensed the S8 process technology; traceability markings presumably tell where the device came from but this isn't known yet.
   * Cortex-M0 CPU at up to 48 MHz
@@ Line 10: / Line 10: @@
   * 4 Universal Digital Blocks (UDBs, basically CPLD function blocks)
-Looks like 130 nm or smaller tech with >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison with CoolRunner-2 architecture is pending.
+Confirmed by SEM imaging to be 130nm tech, layer count not measured.
+Looks like >= 4 metal layers (thick top metal, at least one vertical-horizontal routing pair, then M1). Full delayering and side-by-side comparison of the UDBs vs CoolRunner-2 architecture is pending.
 ====== Package ======
@@ Line 26: / Line 28: @@
 ====== Die ======
+===== Top metal =====
 Size is approximately 2120 x 3210 μm (6.80 mm<sup>2</sup>)
-Overview
+Die overview. Bond pads are mostly grouped into blocks of 9, most likely one ground and eight I/O. The isolated ones in the upper right are probably power, the four at bottom left are probably port 4 since it only has four pins and lacks an associated ground. A full pinout could likely be recovered fairly easily by going clockwise from this block.
 {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_bf_neo10x_3k.jpg?600|}}
@@ Line 50: / Line 54: @@
 {{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_25_bf_neo40x_annotated.jpg?600|}}
+===== Active area =====
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_bf_neo10x_2k_annotated.jpg?600|}}
+Boot ROM
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_19_bf_neo40x_annotated.jpg?600|}}
+I/O cell
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_20_bf_neo40x_annotated.jpg?600|}}
+NOR Flash. Interesting structure, haven't seen this before.
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_21_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_01.jpg?600|}}
+Random logic
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_22_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_02.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_03.jpg?600|}}
+Mysterious small SRAM blocks... FIFOs?
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_active_23_bf_neo40x_annotated.jpg?600|}}
+UDB area
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_03_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_07.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_08.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_09.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_10.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_11.jpg?600|}}
+SRAM block. Single port 6T cells.
+{{:azonenberg:cypress:cy8c4245axi:cy8c4245axi_delayer_04_bf_neo40x_annotated.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_05.jpg?600|}}
+{{:azonenberg:cypress:cy8c4245axi:psoc4_06.jpg?600|}}
+Analog block. Comparator?
+{{:azonenberg:cypress:cy8c4245axi:psoc4_13.jpg?600|}}
+More random memory. Looks like a different 6T cell, possibly another IP library?
+{{:azonenberg:cypress:cy8c4245axi:psoc4_14.jpg?600|}}